Quantum Error Correction in Donor Spins in Silicon
Quantum Error Correction (QEC) is essential for developing scalable, useful quantum computers.
Quantum Error Correction (QEC) is essential for developing scalable, useful quantum computers. QEC is not hardware-agnostic; each type of hardware has its own advantages and disadvantages, which must be considered when implementing QEC strategies. In this context, implanted donor spins in silicon are interesting due to their compatibility with CMOS technology, enhanced connectivity beyond nearest-neighbors, and clean Hamiltonians that do not require extensive adjustments. In our lab, we explore how to implement QEC scenarios in a resource-efficient way by delving into the specifics of our hardware, designing experiments, and investigating scalability paths for building useful silicon quantum computers.
One such project, which we have theoretically developed and published in Quantum Science and Technology [Üstün et al 2024 Quantum Sci. Technol. 9 035037, (2024)], is the Single-Step Parity Check (SSPC) Gate Set for QEC. This work enables the implementation of parity check circuits in a single step with one gate (one pulse), eliminating the need to decompose the process into sequential CNOT gates. Since parity check circuits are fundamental to QEC and are traditionally implemented using sequential one- and two-qubit gates, this method represents a significant advancement. This is especially useful for the Honeycomb code, which requires only two-body parity checks. Our hardware naturally implements these two-body parity check circuits in a single step, increasing the error threshold by nearly three times compared to the surface code, as demonstrated in Gidney's work [Gidney et al. Quantum 5, 605 (2021)].
This example demonstrates increasing the error threshold by reducing circuit gates. Here we create two circuits with different error rates to achieve approximately the same perfection rate. (a) A traditional XX parity check circuit with Hadamard and identity gates as single-qubit gates, and CNOT gates as two-qubit gates. The circuit is modeled using a standard Pauli based noise model where errors are randomly chosen over X, Y and Z for single qubit gates (including idling gates, initialisation and measurement) and over the 15 possible combination of two-qubit Pauli operators for all two qubit gates, applied with a probability. Each single-qubit gate is created with p = 0.0085 (corresponding to 99.43% fidelity). Errors calculated in stochastic Pauli channels yield a total perfection rate of at the circuit's end. (b) Using a direct XX parity check gate with an XX-SSPC gate, we can tolerate a much larger phase-flip error rate per qubit, p = 0.0239 to achieve a similar perfection rate as in (a).
Image by Gozde Ustun: Increasing Error Threshold by using the SSPC gate set
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Gözde Üstün, Andrea Morello and Simon Devitt 2024 Single-step parity check gate set for quantum error correction.
Simon Devitt at University of Technology, Sydney.